Fifteenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2010)
Sheraton Station Square
Pittsburgh, PA - March 13~17, 2010

Accepted Student Posters

  • Automatic Hardware Execution Throttling for Multi-core Resource Management, Xiao Zhang, Rongrong Zhong, Sandhya Dwarkadas, Kai Shen (University of Rochester)
  • LSA: Streaming Processing in General Purpose Processor, Libo Huang, Zhiying Wang, Xin Zhang (National University of Defense Technology)
  • Using Pattern Sampling to Simplify and Improve L2 Caches, Yingying Tian, Samira Khan, Daniel A. Jiménez (University of Texas at San Antonio)
  • Best-Effort Parallel Execution Framework for Recognition and Mining Applications, Jiayuan Meng (NEC Labs America and University of Virginia), Anand Raghunathan (NEC Labs America and Purdue University), Srimat Chakradhar (NEC Labs America), Surendra Byna (NEC Labs America)
  • Language and Compiler Extensions for Heterogeneous Computing, Albert Sidelnik, Maria Jesus Garzaran, David Padua (University of Illinois at Urbana-Champaign), Bradford L. Chamberlain (Cray Inc.)
  • The Data Pump Architecture for Algorithm-Specific DSP Processor/Program Co-Synthesis, Qian Yu, Daniel S. McFarlin, Douglas Jones, Albert Sidelnik, Brandon Moore, Franz Franchetti, María Garzarán, James C. Hoe, Markus Püschel, David Padua, José M.F.Moura (Carnegie Mellon University)
  • Energy-efficient NoC Design for CMP Systems, Pingqiang Zhou, Jieming Yin, Antonia Zhai, Sachin S. Sapatnekar (University of Minnesota)
  • Understanding Performance using Code Reordering, Zhe Wang, Daniel A. Jiménez (University of Texas at San Antonio)
  • Transparent Fault Isolation in Plugins using Dynamic Compilation, Peter Feiner, Angela Demke Brown, Ashvin Goel (University of Toronto)
  • A Composition Kernel: Towards Multicore Embedded Systems, Yuki Kinebuchi, Alexandre Courbot, Hiromasa Shimada, Tatsuo Nakajima (Waseda University)
  • ROSY: A Fully-Software Solution to Recover from Hard Errors, R Karthik Raghavan, V. Kamakoti (Indian Institute of Technology Madras)
  • Accurate and Efficient Process Scheduling among Virtual Machines, Hidekazu Tadokoro (Tokyo Institute of Technology), Kenichi Kourai (Kyushu Institute of Technology, JST CREST), Shigeru Chiba (Tokyo Institute of Technology)
  • Reliability and Security Issues in Multiple OS Environments for Future Embedded Systems, Hiromasa Shimada, Yuki Kinebuchi, Alexandre Courbot, Tatsuo Nakajima (Waseda University)
  • Safe Binary Device Driver Reuse via User-level Binary Translation, Rong Chen, Zhijun Hao, Kang Liu, Haibo Chen, Binyu Zang (Fudan University)
  • Hybrid TM Using NOrec STM, Luke Dalessandro (University of Rochester), Michael F. Spear (Lehigh University), Michael L. Scott (University of Rochester)
  • Hypervisor-based Prototyping of Disaggregated Memory and Benefits of VM Consolidation, Kevin Lim (University of Michigan, Ann Arbor), Jichuan Chang (Hewlett-Packard Labs), (Jose Renato Santos) Hewlett-Packard Labs, (Yoshio Turner) Hewlett-Packard Labs, Trevor Mudge (University of Michigan, Ann Arbor), Parthasarathy Ranganathan (Hewlett-Packard Labs), Steven Reinhardt (Advanced Micro Devices and University of Michigan, Ann Arbor), Thomas Wenisch (University of Michigan, Ann Arbor)
  • Power Management for Fine-grain Parallel Workloads in a Many-core Processor, Fuat Keceli (Univ. of Maryland), Tali Moreshet (Swarthmore College), Uzi Vishkin (Univ. of Maryland)
  • Design of Throughput-optimized Arrays for Regular Loops, Arpith C. Jacob (Washington University in St. Louis)
  • Hybrid Prefetcher with Dynamic Accuracy and Coverage Control, Yasuo Ishii (University of Tokyo)
  • Exploiting Parallelism in Client-side JavaScript Applications, Mojtaba Mehrara, Mehrzad Samadi, and Scott Mahlke (University of Michigan)
  • Detecting Processor Instruction Cache for Platform Aware Compilation, Jeffrey A. Sandoval, Keith D. Cooper, Timothy J. Harvey (Rice University)
  • Ally: OS-Transparent Packet Inspection Using Sequestered Cores, Jen-Cheng Huang (Georgia Tech), Matteo Monchiero (HP Labs), Yoshio Turner (HP Labs)
  • Optimizing Dynamic Types for JavaScript Just-in-Time Compiler, Jin-Seok Oh (Seoul National University)
  • Resource-Aware Compiler Prefetching for Many-Cores, George C. Caragea, Alexandros Tzannes, Fuat Keceli, Rajeev Barua, Uzi Vishkin (University of Maryland)
  • PAW: Profiling of All-Window Footprints, Xiaoya Xiang, Chen Ding (University of Rochester)
  • Solutions to Open Problems in Using Machine Learning to Construct Intelligent Compilers, Eunjung Park, Sameer Kulkarni, Sandeep Nagaraj, and John Cavazos (University of Delaware)
  • Multi-Client Web Proxy Cache on A Low-Power Wireless Router, Amal Fahad, Kai Shen (University of Rochester)
  • Dependence Hints For Behavior-oriented Program Parallelization, Tongxin Bai, Bryan Jacobs, Chen Ding (University of Rochester)
  • SRAM/DRAM Hybrid Cache Architecture and Its Adaptive Optimization for 3D Integrated Microprocessors, Shinya Hashiguchi, Takatsugu Ono, Koji Inoue, Kazuaki Murakami (Kyushu Univercity, Japan)
  • Static Reuse Distances for Locality-based Optimizations in MATLAB, Chun-Yu Shei, Arun Chauhan (Indiana University Bloomington)
  • LambdaSignatures: Mining Code Behavior for Reducing Compiler Design Effort, John Demme, Simha Sethumadhavan (Columbia University)

Instruction for Poster Authors

  • Please print your poster (portrait) on 24in width X 34in height (61cm x 86cm) paper and bring the poster with you to the conference.
  • The poster session will begin at 6:30pm on Sunday. Information about the poster session location will be available at the registration desk.
  • Please come to the room for the poster session at 5:30pm for setting up your poster. Easels and foam cores will be provided by the conference and will already be set up for you. On every foam core, there will be a note showing the poster ID, title, and author list. Please set up your poster on the corresponding foam core.
  • There will not be any formal speech at the beginning of the poster session. The poster session will begin naturally as the opening reception starts.