Analysis and Mitigation of the Impact of Process Variations on 3D Microarchitectures

Tuesday December 4, 2007
Hamerschlag Hall D-210
4:30 pm

Siddharth Garg
Carnegie Mellon University

Three-dimensional (3D) die-stacking technology is an emerging solution to the increasing interconnect delay problems that arise in deep sub-micron manufacturing processes. While the static performance benefits of moving to a 3D design style have been extensively studied before, the impact of process variations on 3D designs has not been investigated. In this talk, we propose a micro-architecture level model to analyze the impact of process variations on the maximum frequency of 3D designs, and show that process variations can lead to larger performance degradation for 3D designs as compared to their conventional 2D counterparts.

To regain some of the performance lost to process variations, we also propose a performance-driven die-level 3D integration strategy that maximizes the number of manufactured 3D systems that meet a specified performance constraint. The advantages of the proposed strategy are investigated for the case of application-specific and general-purpose multi-processor systems.

Siddharth is a Ph.D. candidate in the Department of Electrical and Computer Engineering, where he is advised by Prof. Diana Marculescu. He received a B.Tech. in Electrical Engineering from the Indian Institute of Technology (Madras) in 2004, and an MS in Electrical Engineering from Stanford University in 2005. His research interests include variability- and reliability-aware design methodologies. He enjoys referring to himself in the third person.