Compiler Optimization of Memory-Resident Value Communication Between Speculative Threads

Tuesday March 2, 2004
Hamerschlag Hall D-210
4:00 pm

Antonia Zhai
Carnegie Mellon University

Thread-level speculation facilitates the parallelization of general-purpose applications by allowing potentially dependent threads to run speculatively in parallel. Efficient inter-thread value communication is essential for improving performance in TLS. Although several value communication mechanisms using hardware support have been proposed, relatively little work has been done to exploit the potential of compilers. Building on recent research on compiler optimization for scalar value communication, we study compiler techniques for communicating memory-resident values.

In this talk, I will discuss how the compiler is able to automatically identify frequently-occurring memory-resident data dependences, and insert synchronization for communicating values and preserving correctness. A comparison between compiler-inserted synchronization and hardware-inserted synchronization reveals that the hardware and the compiler are complementary and should work in tandem.

Antonia Zhai is a Ph.D. candidate in the Department of Computer Science at Carnegie Mellon University. She received her B.A.Sc. and M.A.Sc. in Computer Engineering from the University of Toronto in 1996 and 1998 respectively. Currently, she is a member of the STAMPede project led by Todd Mowry. Her thesis research focuses on developing advanced compiler technology to exploit the potential of thread-level speculation for general-purpose applications. Her areas of interests include programming language, compiler optimization, computer architecture and pervasive computation/communication systems.