Reconciling Personal Experience with Conventional Wisdom around FPGAs, Derek Chiou (Microsoft)

Tuesday November 12, 2019
Location: Doherty Hall 1112
Time: 12:00PM-1:00PM

Conventional wisdom says that FPGAs are an order of magnitude lower in frequency, larger in area, and higher in power than ASICs and, therefore, are only appropriate when volumes are very low or for prototyping on the way to building an ASIC. I have, however, developed and deployed FPGA solutions that are much closer to parity (and sometimes better than parity) with silicon that are normally called ASICs. In this talk, I will discuss some of those examples and describe why the standard comparison methodologies are flawed and how they can be improved. I will then present current results that compare (i) FPGA implementations to ASICs and (ii) FPGAs with overlays and an OpenCL programming model to GPUs.

Derek Chiou is a Partner Architect at Microsoft responsible for infrastructure hardware architecture and future uses of FPGAs and a Research Scientist in the Electrical and Computer Engineering Department at The University of Texas at Austin. He co-started the Azure SmartNIC effort and lead the Bing FPGA team to first deployment of Bing ranking on FPGAs. Until 2016, he was an associate professor at UT. Before going to UT, Dr. Chiou was a system architect at Avici Systems, a manufacturer of terabit core routers. Dr. Chiou received his Ph.D., S.M. and S.B. degrees in Electrical Engineering and Computer Science from MIT.