Accelerating Visual Inertial Odometry

Thursday May 2, 2019
Location: HH 1107
Time: 12:00PM-1:00PM

Abstract

Visual Inertial Odometry (VIO) is used for estimating pose and trajectory of a system and is a foundational requirement in many emerging applications like AR/VR, Autonomous navigation in cars, drones and robots. In this talk I shall discuss analyzed key compute bottlenecks in VIO and following a hardware-software co-design approach, propose novel micro-architectural techniques that optimize compute, dataflow, bandwidth and dynamic power to make it possible to implement ultra-low latency VIO even on a cost and power budget constrained edge device. Acceleration and offload of linear algebra tasks enables high (e.g. kilo hertz) sample rate IMU usage in VIO processing while acceleration of image processing pipe increases precision, robustness and reduces IMU induced drift in final pose estimate. The proposed accelerator requires a small silicon footprint (1.3 mm2 in a 28nm process at 600 MHz), utilizes a modest on-chip shared SRAM (560KB) and achieves 10x speedup (compared to a software-only implementation) in image sample-based pose update latency while consuming just 2.2 mW power. In our FPGA implementation, using EuRoC VIO dataset (VGA 30fps images and 100Hz IMU) we achieve pose estimation accuracy (loop closure error) comparable to a software based VIO implementation.

Bio

Gurpreet Singh Kalsi is working as a Research Scientist at Intel’s PAR (Processor Architecture Research) Lab. Before joining Research Lab in 2015 he was working as Graphics Micro-architect at Intel’s VPG (Visual and Parallel computing Group) group. He has over 15 years of experience in Microarchitecture and Design of 3D Graphics, Memory controllers and Computer Vision accelerators and has in depth knowledge and years of contribution towards ASIC cycle from spec to silicon and expertise in Low-power design techniques. He holds several patents and few more filed in the domain on microarchitecture and efficient floating point compute circuits. Before joining Intel in 2005 he worked with CDAC (Centre for Development of Advanced Computing) India contributing towards development of Network Interface Card for India’s PARAM Supercomputer.

He has published few papers at Intel conferences in the field of Low-Power microarchitecture and design practices. He is awarded with VPG top award for 3 times in 2012/13/15 for contribution towards doubling the rendering pipeline throughput, reducing Cdyn by 20% for Skylake and designing highly complex input assembler block with quality. He was awarded Master’s degree in 2002 specializing in microelectronics from Kurukshetra University, India. His research interest spans across exploring efficient Microarchitecture and Compute Components for emerging technologies like Machine Learning, Computer Vision, Genomics etc. mapping them to newer platforms like PiM, 3D Memories etc. and help them to shape as a product.