Accelerating Microsoft's Cloud, Derek Chiou (Microsoft)

Tuesday November 12, 2019
Location: CIC 4th floor Panther Hollow Conference Room
Time: 4:30PM-6:00PM

This talk describes Microsoft’s balanced acceleration efforts that include FPGAs and ASICs. FPGAs provide programmability with hardware performance, while ASICs provide density, power, and cost advantages for fixed functions. Two examples, specifically, the SmartNIC effort accelerating Azure's network using FPGAs and the Corsica Project Zipline compression ASIC, will be described. Microsoft is moving towards open accelerator eco-systems as demonstrated by the release of the Project Zipline compression standard with RTL code.

Derek Chiou is a Partner Architect at Microsoft responsible for infrastructure hardware architecture and future uses of FPGAs and a Research Scientist in the Electrical and Computer Engineering Department at The University of Texas at Austin. He co-started the Azure SmartNIC effort and lead the Bing FPGA team to first deployment of Bing ranking on FPGAs. Until 2016, he was an associate professor at UT. Before going to UT, Dr. Chiou was a system architect at Avici Systems, a manufacturer of terabit core routers. Dr. Chiou received his Ph.D., S.M. and S.B. degrees in Electrical Engineering and Computer Science from MIT.