Multiversioned Page Overlays: Enabling Faster Serializable Hardware Transactional Memory

Wednesday September 18, 2019
Location: CIC 4th floor Panther Hollow Conference Room
Time: 4:30PM-6:00PM

Practical and efficient support for multiversioning memory systems would offer a number of potential advantages, including improving the performance and functionality of hardware transactional memory (HTM). This practice talk presents a new approach to multiversioning support (Multiversioned Page Overlays) along with a new HTM design that it enables: OverlayTM. Compared with existing HTM designs, OverlayTM takes advantage of multiversioning to reduce unnecessary transaction aborts while providing full serializable semantics (in contrast with multiversioning HTMs that improve performance at the expense of being vulnerable to write skew anomalies). Our performance results demonstrate that OverlayTM is especially advantageous in read-heavy workloads.

The paper on OverlayTM has been accepted to the 2019 conference of Parallel Architecture and Compiler Technologies (PACT).

Ziqi Wang is a third-year PhD student working with Professor Todd Mowry. His research interest includes Computer Architecture, High-Performance Parallel Computing, Database Systems, and Transaction Processing. The current project, OverlayTM, extends the hardware Page Overlays framework to provide a powerful multiversioned abstraction of the main memory. Prior to joining the PhD program, Ziqi has been working closely with Professor Andy Pavlo as a Masters student on the topic of efficient in-memory lock-free indexing.