|
:: Digital Sandbox Annual Workshop 2004, 11/02/04 In August, Digital Sandbox held its Third Annual Workshop for the participating faculty, staff and The Digital Greenhouse members. Please review the following presentations from the Workshop: :: Digital Sandbox released "ASIC
design with EDA software" live demonstrations, 04/07/04
To assist the SDX students in dealing with steep learning curve of
the modern ASIC design flow, Digital Sandbox designed and released 10
live demonstrations on how to use various EDA tools used in the
class. The demos show in detail how to launch, use, design and run
the tools on local machines, they also provide sample scripts and
tutorials for a quick jump start. The demos released include:
:: Sandbox Design Experience course has started, 15/01/04 Sandbox Design Experience is a graduate-level course offered concurrently in three universities, Carnegie Mellon, University of Pittsburgh and Pennsylvania State University. The SDX course is a project-based course in which over 50 students follow state of the art ASIC design methodology to design a large multimillion-gate design. This year the students design Low Density Parity Check decoder that conforms with IEEE 802.11g standard using Network-on-Chip design methodology. According to the specification given, students will design 100 Mbps LDPC decoder that will occupy less than two square centimeters. The design is performed with OKI 0.16um standard cell library, Virage RAM and Artisan ROM blocks. EDA design flow includes Mentor Graphics Modelsim, Verisity Specman, Synopsys Design Compiler, PrimeTime, Power Compiler and Cadence Silicon Ensemble. Digital Sandbox provides complete EDA tool support for the class. :: Digital Sandbox rolls out several standard cell libraries,10/30/03 Digital Sandbox received new and upgraded std. cell libraries from STMicro for 0.09um, 0.13um and 0.18um process. These libraries have been installed on Andrew File System (AFS) and all files required for synthesis and place and route were generated. In addition, we offer access to OKI Semiconductor 0.16um, CMU 0.18um, VTVT 0.25um and Generic Cadence libraries. :: Full-Custom design flow is now fully supported, 10/01/03 :: Annual Digital Sandbox Workshop, 08/13/03
Carnegie Mellon Standard Cell Library for TSMC 0.18um process is nearing its first release. We have completed the layout, characterization and abstract generation for all cells. The library is now integrated with standard front and back-end flows, i.e. Synopsys Design Compiler, Cadence Silicon Ensemble and Monterey Dolphin. Most of the work in the project was done by two ECE undergraduates, Zack Menegakis and Steve Beigelmacher with CAD support from Max Khusid and Tom Kroll. Please stay tuned for the official release and download information. :: CAD FAQ officially released, 08/05/03 CAD FAQ, our knowledgebase for for VLSI CAD software being used at Carnegie Mellon, is now online. Please read more about it here. The database is accessible for the participating univerisities: Carnegie Mellon, University of Pittsburgh and PennState. :: Launching the new Digital Sandbox website, 08/01/2003 The new official Digital Sandbox website has been launched. We would like to thank ECE Multimedia design team and especially Christa Jones for the website design, templates and graphics. |