Starting June 2021, the generated Verilog files are available under BSD 3-clause Clear license.
CONNECT is a flexible RTL generator for fast, FPGA-friendly Networks-on-Chip. This website serves as a front-end to CONNECT's network generation framework, which is primarily based on Bluespec SystemVerilog. All networks generated through CONNECT consist of fully synthesizable Verilog.
CONNECT supports a variety of common network topologies, as well as custom user-configured networks, that can be either specified through special configuration files or created through the CONNECT Network Editor. A variety of network and router parameters, such as the router type, pipelining options, the number of virtual channels or allocator type, allow the user to further customize the network and trade-off between resource usage and performance to satisfy application-specific requirements.
Our 2012 FPGA paper describes an initial version of the CONNECT NoC architecture and includes detailed synthesis and performance results for various CONNECT FPGA-based NoCs. The original codebase for CONNECT is partially based on our award-winning entry in the MEMOCODE 2011 Hardware/Software Codesign contest. For more information on our contest entry please see our invited MEMOCODE 2011 paper.
Feel free to try CONNECT using the web-based generator below. Code generation can take from a few minutes up to a few hours depending on the network size and router complexity. A tarball containing the Verilog RTL and other supporting material will be sent as an attachment to the provided email address. The results generated through CONNECT are provided under a BSD 3-clause Clear license. Please click here for the full license terms. For any questions or comments please contact Michael Papamichael at - any feedback/suggestions on architectural and micro-architectural improvements will be considered for future incorporation.