Main Program

Sunday, June 14, 2015
PM
17:00-18:00
Welcome Reception (Oregon 201-202)
 
18:00-19:15
Dr. Michael Stonebraker, Massachusetts Institute of Technology

Monday, June 15, 2015
AM
7:15-8:00
Breakfast (Hall A)
 
8:00-8:15
Opening Remarks (Oregon 201-202)
 
8:15-8:45
Fast Forward Session I (Oregon 201-202)
 
8:45-10:00
Session 1 (Oregon 201-202): Datacenter Architectures I
 
10:00-10:20
Break (Oregon Ballroom Lobby)
 
10:20-11:10
Session 2A (Oregon 203): GPUs I
Session 2B (Oregon 204): Virtual Memory Management
 
11:10-12:30
Plenary Talk I (Exhibit Hall A)
PM
12:30-13:50
Lunch (Exhibit Halls A1-B)
 
13:50-15:30
Session 3A (Oregon 203): Accelerators I
Session 3B (Oregon 204): Performance Analysis and Tools
 
15:30-16:00
Break (Oregon Ballroom Lobby)
 
16:00-17:40
Session 4A (Oregon 203): DRAM Caches and Architectures
Session 4B (Oregon 204): Processor Architecture I
 
17:40
Adjourn
 
18:00-onwards
Business Meeting (Oregon 201-202)

Tuesday, June 16, 2015
AM
7:15-8:00
Breakfast (Hall A)
 
8:00-8:45
Fast Forward Session II (Oregon 201-202)
 
8:45-10:00
Session 5 (Oregon 201-202): Processor Architecture II
 
10:00-10:20
Break (Oregon Ballroom Lobby)
 
10:20-11:10
Session 6A (Oregon 203): Memory Systems I
Session 6B (Oregon 204): Security and Virtualization
 
11:10-12:30
Plenary Talk II (Exhibit Hall A)
PM
12:30-14:30
Awards Luncheon (Portland Ballroom 251/257/258)
 
14:30-16:10
Session 7A (Oregon 203): Parallel Architectures
Session 7B (Oregon 204): Datacenter Architectures II
 
16:10
Adjourn
 
16:45-onwards
Banquet and Excursion (World Forestry Center)

Wednesday, June 17, 2015
AM
7:15-8:00
Breakfast (Hall A)
 
8:20-10:00
Session 8 (Oregon 201-202): GPUs II
 
10:00-10:20
Break (Oregon Ballroom Lobby)
 
10:20-11:10
Session 9A (Oregon 203): Accelerators II
Session 9B (Oregon 204): Networks and Storage
 
11:10-12:30
Plenary Talk III (Exhibit Hall A)
PM
12:30-13:50
Lunch (Exhibit Halls A1-B)
 
13:50-15:05
Session 10A (Oregon 203): Security
Session 10B (Oregon 204): Mobile and Embedded Systems
 
15:05-15:30
Break (Oregon Ballroom Lobby)
 
15:30-16:45
Session 11A (Oregon 203): Dependable Architectures
Session 11B (Oregon 204): Memory Systems II
 
16:45
Adjourn
 
Sunday, June 14, 2015
 
Sunday, 18:00-19:15
Turing Award Lecture, Dr. Michael Stonebraker, Massachusetts Institute of Technology
  • Michael Stonebraker is being recognized for fundamental contributions to the concepts and practices underlying modern database systems. Stonebraker is the inventor of many concepts that were crucial to making databases a reality and that are used in almost all modern database systems. His work on INGRES introduced the notion of query modification, used for integrity constraints and views. His later work on Postgres introduced the object-relational model, effectively merging databases with abstract data types while keeping the database separate from the programming language.

    Stonebraker's implementations of INGRES and Postgres demonstrated how to engineer database systems that support these concepts; he released these systems as open software, which allowed their widespread adoption and their code bases have been incorporated into many modern database systems. Since the pathbreaking work on INGRES and Postgres, Stonebraker has continued to be a thought leader in the database community and has had a number of other influential ideas including implementation techniques for column stores and scientific databases and for supporting on-line transaction processing and stream processing.
 
Monday, June 15, 2015
 
 
Monday, 8:45-10:00
Session 1: Datacenter Architectures I
Chair: José Martínez
 
  • BlueDBM: An Appliance for Big Data Analytics
    • Sang-Woo Jun (MIT), Ming Liu (MIT), Sungjin Lee (MIT), Jamey Hicks (Quanta Research Cambridge), John Ankcorn (Quanta Research Cambridge), Myron King (Quanta Research Cambridge), Shuotao Xu (MIT), and Arvind (MIT)
     
  • Towards Sustainable In-Situ Server Systems in the Big Data Era
    • Chao Li (Shanghai Jiao Tong University/University of Florida), Yang Hu (University of Florida), Longjun Liu (Xi'an Jiaotong University/University of Florida), Juncheng Gu (University of Florida), Mingcong Song (University of Florida), Xiaoyao Liang (Shanghai Jiao Tong University), Jingling Yuan (Wuhan University of Technology), and Tao Li (University of Florida)
     
  • DjiNN and Tonic: DNN as a Service and Its Implications for Future Warehouse Scale Computers
    • Johann Hauswald, Yiping Kang, Michael A. Laurenzano, Quan Chen, Cheng Li, Trevor Mudge, Ronald G. Dreslinski, Jason Mars, and Lingjia Tang (University of Michigan)
     
Monday, 10:20-11:10
Session 2A: GPUs I
Chair: Wen-mei Hwu
 
  • A Case for Core-Assisted Bottleneck Acceleration in GPUs: Enabling Flexible Data Compression with Assist Warps
    • Nandita Vijaykumar (CMU), Gennady Pekhimenko (CMU), Adwait Jog (Pennsylvania State University), Abhishek Bhowmick (CMU), Rachata Ausavarungnirun (CMU), Chita Das (Pennsylvania State University), Mahmut Kandemir (Pennsylvania State University), Todd C. Mowry (CMU), and Onur Mutlu (CMU)
     
  • Harmonia: Balancing Compute and Memory Power in High-Performance GPUs
    • Indrani Paul (AMD/Georgia Tech), Wei Huang (AMD), Manish Arora (AMD/UCSD), and Sudhakar Yalamanchili (Georgia Tech)
     
Monday, 10:20-11:10
Session 2B: Virtual Memory Management
Chair: Mattan Erez
 
  • Redundant Memory Mappings for Fast Access to Large Memories
    • Vasileios Karakostas (Barcelona Supercomputing Center/UPC), Jayneel Gandhi (University of Wisconsin-Madison), Furkan Ayar (Dumlupinar University), Adrian Cristal (Barcelona Supercomputing Center/UPC), Mark D. Hill (University of Wisconsin-Madison), Kathryn S. McKinley (Microsoft Research), Mario Nemirovsky (Barcelona Supercomputing Center), Michael M. Swift (University of Wisconsin-Madison), and Osman Unsal (Barcelona Supercomputing Center)
     
  • Page Overlays: An Enhanced Virtual Memory Framework to Enable Fine-grained Memory Management
    • Vivek Seshadri (CMU), Gennady Pekhimenko (CMU), Olatunji Ruwase (Microsoft), Onur Mutlu (CMU), Phillip B. Gibbons (Intel), Michael A. Kozuch (Intel), Todd C. Mowry (CMU), and Trishul Chilimbi (Microsoft)
     
Monday, 13:50-15:30
Session 3A: Accelerators I
Chair: Bill Dally
 
  • ShiDianNao: Shifting Vision Processing Closer to the Sensor
    • Zidong Du (Chinese Academy of Sciences), Robert Fasthuber (EPFL), Tianshi Chen (Chinese Academy of Sciences), Paolo Ienne (EPFL), Ling Li (Chinese Academy of Sciences), Tao Luo (Chinese Academy of Sciences), Xiaobing Feng (Chinese Academy of Sciences), Yunji Chen (Chinese Academy of Sciences), and Olivier Temam (INRIA)
     
  • A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing
    • Junwhan Ahn (Seoul National University), Sungpack Hong (Oracle), Sungjoo Yoo (Seoul National University), Onur Mutlu (CMU), and Kiyoung Choi (Seoul National University)
     
  • Efficient Execution of Memory Access Phases Using Dataflow Specialization
    • Chen-Han Ho, Sung Jin Kim, and Karthikeyan Sankaralingam (University of Wisconsin-Madison)
     
  • Data Reorganization in Memory Using 3D-stacked DRAM
    • Berkin Akin, Franz Franchetti, and James C. Hoe (CMU)
     
Monday, 13:50-15:30
Session 3B: Performance Analysis and Tools
Chair: Natalie Enright Jerger
 
  • Quantitative Comparison of Hardware Transactional Memory for Blue Gene/Q, zEnterprise EC12, Intel Core, and POWER8
    • Takuya Nakaike (IBM), Rei Odaira (IBM), Matthew Gaudet (IBM), Maged M. Michael (IBM), and Hisanobu Tomari (University of Tokyo)
     
  • Profiling a warehouse-scale computer
    • Svilen Kanev (Harvard), Juan Pablo Darago (Universidad de Buenos Aires), Kim Hazelwood (Yahoo), Parthasarathy Ranganathan (Google), Tipp Moseley (Google), Gu-Yeon Wei (Harvard), and David Brooks (Harvard)
     
  • Computer Performance Microscopy with SHIM
    • Xi Yang (Australian National University), Stephen M. Blackburn (Australian National University), and Kathryn S. McKinley (Microsoft)
     
  • Flexible Software Profiling of GPU Architectures
    • Mark Stephenson (NVIDIA), Siva Hari (NVIDIA), Yunsup Lee (NVIDIA/UC Berkeley), Eiman Ebrahimi (NVIDIA), Daniel Johnson (NVIDIA), David Nellans (NVIDIA), Mike O'Connor (NVIDIA/UT-Austin), and Stephen W. Keckler (NVIDIA/UT-Austin)
     
 
Monday, 16:00-17:40
Session 4A: DRAM Caches and Architectures
Chair: Steve Keckler
 
  • BEAR: Techniques for Mitigating Bandwidth Bloat in Gigascale DRAM Caches
    • Chiachen Chou (Georgia Tech), Aamer Jaleel (NVIDIA), and Moinuddin K. Qureshi (Georgia Tech)
     
  • A Fully Associative, Tagless DRAM Cache
    • Yongjun Lee (Sungkyunkwan University), Jongwon Kim (Sungkyunkwan University), Hakbeom Jang (Sungkyunkwan University), Hyunggyun Yang (POSTECH), Jangwoo Kim (POSTECH), Jinkyu Jeong (Sungkyunkwan University), and Jae W. Lee (Sungkyunkwan University)
     
  • Multiple Clone Row DRAM: A Low Latency and Area Optimized DRAM
    • Jungwhan Choi (KAIST), Wongyu Shin (KAIST), Jaemin Jang (KAIST), Jinwoong Suh (KAIST), Yongkee Kwon (SK Hynix), Youngsuk Moon (SK Hynix), and Lee-Sup Kim (KAIST)
     
  • Flexible Auto-Refresh: Enabling Scalable and Energy-Efficient DRAM Refresh Reductions
    • Ishwar Bhati (Oracle), Zeshan Chishti (Intel), Shih-Lien Lu (Intel), and Bruce Jacob (University of Maryland)
     
 
Monday, 16:00-17:40
Session 4B: Processor Architecture I
Chair: Radu Teodorescu
 
  • Cost-Effective Speculative Scheduling in High Performance Processors
    • Arthur Perais (INRIA), Andréeznec (INRIA), Pierre Michaud (INRIA), Andreas Sembrant (Uppsala University), and Erik Hagersten (Uppsala University)
     
  • LaZy Superscalar
    • Gorkem Asilioglu, Zhaoxiang Jin, Murat Koksal, Omkar Javeri, and Soner Onder (Michigan Tech)
     
  • The Load Slice Core Microarchitecture
    • Trevor E. Carlson (Uppsala University), Wim Heirman (Intel), Osman Allam (Ghent University), Stefanos Kaxiras (Uppsala University), and Lieven Eeckhout (Ghent University)
     
  • Semantic Locality and Context-based Prefetching using Reinforcement Learning
    • Leeor Peled (Technion/Intel), Shie Mannor (Technion), Uri Weiser (Technion), and Yoav Etsion (Technion)
     
 
Tuesday, June 16, 2015
 
Tuesday, 8.45-10.00
Session 5: Processor Architecture II
Chair: Ronny Ronen
 
  • Exploring the Potential of Heterogeneous Von Neumann/Dataflow Execution Models
    • Tony Nowatzki, Vinay Gangadhar, and Karthikeyan Sankaralingam (University of Wisconsin-Madison)
     
  • SHRINK: Reducing the ISA Complexity Via Instruction Recycling
    • Bruno Cardoso Lopes, Rafael Auler, Luiz Ramos, Edson Borin, and Rodolfo Azevedo (UNICAMP)
     
  • Branch Vanguard: Decomposing Branch Functionality into Prediction and Resolution Instructions
    • Daniel McFarlin (CMU) and Craig Zilles (UIUC)
     
Tuesday, 10:20-11:10
Session 6A: Memory Systems I
Chair: Karin Strauss
 
  • PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture
    • Junwhan Ahn (Seoul National University), Sungjoo Yoo (Seoul National University), Onur Mutlu (CMU), Kiyoung Choi (Seoul National University)
     
  • SLIP: Reducing Wire Energy in the Memory Hierarchy
    • Subhasis Das (Stanford), Tor M. Aamodt (University of British Columbia), William J. Dally (Stanford/NVIDIA)
     
Tuesday, 10:20-11:10
Session 6B: Security and Virtualization
Chair: Fred Chong
 
  • CloudMonatt: an Architecture for Security Health Monitoring and Attestation of Virtual Machines in Cloud Computing
    • Tianwei Zhang and Ruby B. Lee (Princeton)
     
  • Reducing World Switches in Virtualized Environment with Flexible Cross-world Calls
    • Wenhao Li, Yubin Xia, Haibo Chen, Binyu Zang, and Haibin Guan (Shanghai Jiao Tong University)
     
Tuesday, 14:30-16:10
Session 7A: Parallel Architectures
Chair: Murali Annavaram
 
  • ArMOR: Defending Against Memory Consistency Model Mismatches in Heterogeneous Architectures
    • Daniel Lustig (Princeton), Caroline Trippel (Princeton), Michael Pellauer (NVIDIA), and Margaret Martonosi (Princeton)
     
  • CLEAN: A Race Detector with Cleaner Semantics
    • Cedomir Segulja and Tarek Abdelrahman (University of Toronto)
     
  • MiSAR: Minimalistic Synchronization Accelerator with Resource Overflow Management
    • Ching-Kai Liang and Milos Prvulovic (Georgia Tech)
     
  • Callback: Efficient Synchronization without Invalidation with a Directory Just for Spin-Waiting
    • Alberto Ros (Universidad de Murcia) and Stefanos Kaxiras (Uppsala University)
     
Tuesday, 14:30-16:10
Session 7B: Datacenter Architectures II
Chair: Babak Falsafi
 
  • Thermal Time Shifting: Leveraging Phase Change Materials to Reduce Cooling Costs in Warehouse-Scale Computers
    • Matt Skach (University of Michigan), Manish Arora (UCSD/AMD), Chang-Hong Hsu (University of Michigan), Qi Li (UCSD), Dean Tullsen (UCSD), Lingjia Tang (University of Michigan), and Jason Mars (University of Michigan)
     
  • Heracles: Improving Resource Efficiency at Scale
    • David Lo (Stanford/Google), Liqun Cheng (Google), Rama Govindaraju (Google), Parthasarathy Ranganathan (Google), and Christos Kozyrakis (Stanford)
     
  • HEB: Deploying and Managing Hybrid Energy Buffers for Improving Datacenter Efficiency and Economy
    • Longjun Liu (Xi'an Jiaotong University), Chao Li (Shanghai Jiao Tong University), Hongbin Sun (Xi'an Jiaotong University), Yang Hu (University of Florida), Juncheng Gu (University of Florida), Tao Li (University of Florida), Jingmin Xin (Xi'an Jiaotong University), and Nanning Zheng (Xi'an Jiaotong University)
     
  • Architecting to Achieve a Billion Requests Per Second Throughput on a Single Key-Value Store Server Platform
    • Sheng Li (Intel), Hyeontaek Lim (CMU), Victor Lee (Intel), Jung Ho Ahn (Seoul National University), Anuj Kalia (CMU), Michael Kaminsky (Intel), David Andersen (CMU), Seongil O (Seoul National University), Sukhan Lee (Seoul National University), and Pradeep Dubey (Intel)
     
 
Wednesday, June 17, 2015
 
Wednesday, 8:20am-10:00
Session 8: GPUs II
Chair: David Kaeli
 
  • A Variable Warp Size Architecture
    • Timothy G. Rogers (University of British Columbia), Daniel R. Johnson (NVIDIA), Mike O'Connor (NVIDIA/UT-Austin), and Stephen W. Keckler (NVIDIA/UT-Austin)
     
  • Warped-Compression: Enabling Power Efficient GPUs through Register Compression
    • Sangpil Lee (Yonsei University), Keunsoo Kim (Yonsei University), Gunjae Koo (USC), Hyeran Jeon (USC), Won Woo Ro (Yonsei University), and Murali Annavaram (USC)
     
  • CAWA: Coordinated Warp Scheduling and Cache Prioritization for Critical Warp Acceleration of GPGPU Workloads
    • Shin-Ying Lee, Akhil Arunkumar, and Carole-Jean Wu (Arizona State)
     
  • Dynamic Thread Block Launch: A Lightweight Execution Mechanism to Support Irregular Applications on GPUs
    • Jin Wang (Georgia Tech), Norm Rubin (NVIDIA), Albert Sidelnik (NVIDIA), and Sudhakar Yalamanchili (Georgia Tech)
     
Wednesday, 10:20-11:10
Session 9A: Accelerators II
Chair: Carole Wu
 
  • DynaSpAM: Dynamic Spatial Architecture Mapping using Out of Order Instruction Schedules
    • Feng Liu, Heejin Ahn, Stephen R. Beard, Taewook Oh, and David August (Princeton)
     
  • Rumba: An Online Quality Management System for Approximate Computing
    • Daya S Khudia, Babak Zamirai, Mehrzad Samadi, and Scott Mahlke (University of Michigan)
     
Wednesday, 10:20-11:10
Session 9B: Networks and Storage
Chair: Christopher Batten
 
  • Manycore Network Interfaces for In-Memory Rack-Scale Computing
    • Alexandros Daglis (EPFL), Stanko Novakovic (EPFL), Edouard Bugnion (EPFL), Babak Falsafi (EPFL), and Boris Grot (University of Edinburgh)
     
  • Unified Address Translation for Memory-Mapped SSDs with FlashMap
    • Jian Huang (Georgia Tech), Anirudh Badam (Microsoft), Moinuddin K. Qureshi (Georgia Tech), and Karsten Schwan (Georgia Tech)
     
Wednesday, 13:50-15:05
Session 10A: Security
Chair: Lieven Eeckhout
 
  • FASE: Finding Amplitude-modulated Side-channel Emanations
    • Robert Callan, Alenka Zajic, and Milos Prvulovic (Georgia Tech)
     
  • Probable Cause: The Deanonymizing Effects of Approximate DRAM
    • Amir Rahmati, Matthew Hicks, Daniel E. Holcomb, and Kevin Fu (University of Michigan)
     
  • PrORAM: Dynamic Prefetcher for Oblivious RAM
    • Xiangyao Yu (MIT), Syed Kamran Haider (University of Connecticut), Ling Ren (MIT), Christopher Fletcher (MIT), Albert Kwon (MIT), Marten van Dijk (University of Connecticut), and Srinivas Devadas (MIT)
     
Wednesday, 13:50-15:05
Session 10B: Mobile and Embedded Systems
Chair: Sarita Adve
 
  • MBus: An Ultra-Low Power Interconnect Bus for Next Generation Nanopower Systems
    • Pat Pannuto, Yoonmyung Lee, Ye-Sheng Kuo, Zhi Yoong Foo, Benjamin Kempke, Gyouho Kim, Ronald Dreslinski Jr., David Blaauw, and Prabal Dutta (University of Michigan)
     
  • Accelerating Asynchronous Programs through Event Sneak Peak
    • Gaurav Chadha, Scott Mahlke, and Satish Narayanasamy (University of Michigan)
     
  • VIP: Virtualizing IP Chains on Handheld Platforms
    • Nachiappan Chidambaram Nachiappan (Penn State), Haibo Zhang (Penn State), Jihyun Ryoo (Penn State), Niranjan Soundararajan (Intel), Anand Sivasubramaniam (Penn State), Mahmut Kandemir (Penn State), Ravishankar Iyer (Intel), and Chita R. Das (Penn State)
     
Wednesday, 15:30-16:45
Session 11A: Dependable Architectures
Chair: Milos Prvulovic
 
  • FaultHound: Value-Locality-Based Soft-Fault Tolerance
    • Nitin, Irith Pomeranz, and T. N. Vijaykumar (Purdue)
     
  • COP: To Compress and Protect Main Memory
    • David J. Palframan, Nam Sung Kim, and Mikko H. Lipasti (University of Wisconsin-Madison)
     
  • Hi-fi Playback: Tolerating Position Errors in Shift Operations of Racetrack Memory
    • Chao Zhang (Peking University), Guangyu Sun (Peking University), Xian Zhang (Peking University), Weiqi Zhang (Peking University), Weisheng Zhao (Beihang University), Tao Wang (Peking University), Yun Liang (Peking University), Yongpan Liu (Tsinghua University), Yu Wang (Tsinghua University), and Jiwu Shu (Tsinghua University)
     
Wednesday, 15:30-16:45
Session 11B: Memory Systems II
Chair: Satish Narayanasamy
 
  • Stash: Have Your Scratchpad and Cache it Too
    • Rakesh Komuravelli, Matthew D. Sinclair, Johnathan Alsop, Muhammad Huzaifa, Maria Kotsifakou, Prakalp Srivastava, Sarita V. Adve, and Vikram Adve (UIUC)
     
  • Coherence Protocol for Transparent Management of Scratchpad Memories in Shared Memory Manycore Architectures
    • Lluc Alvarez (Barcelona Supercomputing Center/UPC), Lluis Vilanova (Barcelona Supercomputing Center/UPC), Miquel Moreto (Barcelona Supercomputing Center), Marc Casas (Barcelona Supercomputing Center), Marc Gonzáz (UPC), Xavier Martorell (Barcelona Supercomputing Center/UPC), Nacho Navarro (Barcelona Supercomputing Center/UPC), Eduard AyguadéBarcelona Supercomputing Center/UPC), and Mateo Valero (Barcelona Supercomputing Center/UPC)
     
  • Fusion: Design Tradeoffs in Coherent Cache Hierarchies for Accelerators
    • Snehasish Kumar, Arrvindh Shriraman, and Naveen Vedula (Simon Fraser University)